Method of fabricating and operating single polysilicon flash EEPROM with low positive programming and erasing voltage and small cell size

ABSTRACT

A single polysilicon memory cell ( 10 ) provides a positive low programming and erase voltage together with a small cell size and includes P substrate ( 12 ) and P-well ( 14 ) formed within P substrate ( 12 ). NMOS transistor ( 16 ) is formed within P-well ( 14 ). N +  control gate ( 26 ) is formed in P-well ( 14 ) and includes punch-through implant region ( 26 ). NMOS transistor ( 16 ) and N +  control gate ( 26 ) have in common electrically isolated polysilicon gate ( 22, 32 ) for operating as a floating gate in common with NMOS transistor ( 16 ) and N +  control gate ( 26 ). N +  control gate ( 26 ) includes P-channel punch-through implant ( 34 ) for increasing the capacitive coupling ratio. This improves programming and erasing efficiency within single polysilicon memory cell ( 10 ).

This application is a divisional of application Ser. No. 09/016,616,filed on Jan. 30, 1998, now U.S. Pat. No. 6,054,732.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to semiconductor devices and methods forfabricating such devices and, more particularly, to electronic memorydevices and, even more particularly, to a single polysilicon flashEEPROM capable of using low programming and erasing voltages and formedof a small cell size.

BACKGROUND OF THE INVENTION

Basic input/output systems (BIOS) or microcodes are stored on memorydevices such as EEPROMs and used to control microprocessors and logiccircuits. Today's flexible system-on-system chip architectures requireembedded EEPROMs to make possible easy updates of microcode in systemconfigurations. However, generally, EEPROMs require specialmulti-polysilicon processes and multi-oxidation steps for thin SiO₂layers. Many masks are needed which result in longer process turnaroundtimes, lower yields, higher costs, and lower reliability.

Integration of various different semiconductor fabrication processesinto one specific process generally is complicated and costly. However,K. Ohsaki, et al., “A Single Poly EEPROM Cell Structure for Use inStandard CMOS Processes,” IEEE JOURNAL OF SOLID STATE CIRCUITS, Vol. 29,No. 3, March 1994, describes a single polysilicon EEPROM cell structurethat may be implemented in a standard CMOS process. This structureconsists of adjacently placed NMOS and PMOS transistors with anelectrically isolated common polysilicon gate. The common gate works asa “floating gate” and the structure provides an inversion layer as the“control node (gate).” This EEPROM cell (the “Ohsaki Cell”) may beeasily integrated with CMOS digital an analog circuits, but suffers fromsevere practical limitations.

Limitations associated with the Ohsaki Cell are fundamental in nature.One limitation is that it requires a high programming and erase voltage.Another limitation is that it requires a big cell size. Suffering fromboth of these limitations makes the Ohsaki Cell unacceptable for asimple DRAM fabrication process.

In the conventional single polysilicon EEPROM, a particular problemrelates to erase techniques. One way to erase these existing structuresforces a 5V level on V_(D) and V_(S) and forces a −6V bias on thecontrol gate and substrate. The substrate can tie to −6V or be floating.The erase mechanism that results from this procedure is the result ofdiode breakdown. Unfortunately, this mechanism causes impact ionizationand operates as a hole trap to the floating gate. Thus, the problem withthis method is that a negative voltage is necessary and the substrateneeds to float or tie to the −6V. In this method, a negative charge pumpcircuit is required.

There are other approaches to erasing structures such as the OhsakiCell. One method uses the same type of mechanism as previouslydescribed, but ties the control gate to ground. The substrate is tied to−2V and a very high voltage is forced on the drain and source. Thismethod, unfortunately, produces very poor erase efficiency and resultsin too high a voltage on the source and drain. The high voltage cancause undesirable stress on the EEPROM.

The third method uses an BVCEO breakdown mechanism which causes impactionization and a hold trap to form at the floating gate. This method,unfortunately, also has very poor erase efficiency and for many otherreasons is much less desirable than the two previously describedtechniques.

Another limitation of the Ohsaki Cell and similar structures is the needfor an N-well to serve as the control gate. This design results in alarge EEPROM cell size. With the ever-important design objective ofsmaller memory circuits, the limitation of requiring a large cell sizecan seriously affect the usefulness of the single polysilicon flashEEPROM.

SUMMARY OF THE INVENTION

In light of the above-stated limitations, there is a need for animproved single polysilicon flash EEPROM that provides both low positiveprogramming and erase voltage, as well as provides a small cell size.

The present invention, therefore, provides an improved singlepolysilicon flash EEPROM that overcomes or substantially eliminates theproblems of programming and erase voltages, and larger cell size thatadversely affect the usefulness of known single polysilicon flashEEPROMs.

According to one aspect of the present invention, there is provided asingle polysilicon memory cell for use in CMOS processing and includes aP-substrate, with a P-well formed within the P-substrate, and an NMOStransistor is formed within the P-well. An N⁺ control gate is alsoformed in the P-substrate. The NMOS transistor and the N⁺ control gatehave a polysilicon gate that operates as a floating gate in common withthe NMOS transistor and the N⁺ control gate. The N⁺ control gateincludes a P-channel punch-through implant region for increasing thecapacitive coupling ratio. This improves the programming and erasingefficiency within said single polysilicon memory cell, therebypermitting these voltages to generally decrease.

A technical advantage of the present invention is that no additionalDRAM process steps are needed to produce the reduced size EEPROM cell.Clearly, the ability to achieve this result has significant cost andthroughput benefits for systems that employ the present invention.

Another technical advantage of the present invention is that it providesa smaller EEPROM cell size for minimal channel hot electron (CHE)programming voltage and minimal Fowler-Nordheim (F-N) erase voltage.Because the memory cell of the present invention does not require anN-well, as does the Ohsaki Cell, for example, it consumes less space.The result can be, therefore, that more memory cells formed according tothe teachings of the present invention may be placed in a given layoutarea than is possible with known single polysilicon flash EEPROMs andsimilar devices.

Still, another technical advantage that the present invention providesis both a lower program voltage and a positive only erase voltage. Forexample, in one embodiment of the present invention, the maximum CHEprogram voltage did not exceed 5V, with the threshold voltage shift of2.5V after CHE programming for 100 msec. In addition, this sameembodiment provided a F-N erase voltage of 9V on V_(DD) and V_(SS), withzero volts on V_(PP) and V_(BB).

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and theadvantages thereof, reference is now made to the following descriptionwhich is to be taken in conjunction with the accompanying drawings inwhich like reference numerals indicate like features and wherein:

FIG. 1 illustrates one embodiment of the present invention for channelhot electron (CHE) programming;

FIG. 2 shows an embodiment of the present invention for Fowler-Nordheim(F-N) erasing;

FIG. 3 provides a curve illustrating the drain current-gate voltage timezero curve;

FIG. 4 depicts the floating gate voltage time zero curve;

FIG. 5 graphs the drain current-gate voltage curve after CHE programmingof the present invention;

FIG. 6 shows the drain current-floating gate voltage during programming;

FIG. 7 plots the drain current-gate voltage characteristic of thepresent invention after an F-N erase step; and

FIG. 8 illustrates the drain current-floating gate voltagecharacteristic of the present invention after an F-N erase step.

DETAILED DESCRIPTION OF THE INVENTION

Preferred embodiments of the present invention are illustrated in theFIGUREs like numerals being used to refer to like and correspondingparts of the various drawings.

FIG. 1 illustrates one embodiment of the present invention as a singlepolysilicon Flash EEPROM cell structure 10 that includes withinsubstrate 12. The structure of FIG. 1 is the structure for channel hotelectron (CHE) programming. The single polysilicon Flash EEPROM of thepresent invention operates in a manner similar to that of the previouslydescribed Ohsaki Cell, which description is here incorporated byreference, together with the inventive concepts herein described indetail.

FIG. 2 shows single polysilicon flash EEPROM 10 of the present inventionwhich includes P-well 14 formed in a P-substrate 12. Single polysiliconflash EEPROM 10 can effectively use low programming and erasing voltagesand a small cell size by applying a P-channel transistor punch-throughimplant on the control gate channel area to increase capacitor couplingratio. Thus, in P-substrate 12 is P-well 14 in which is formed N-channeltransistor 16 that includes N⁺ region 18 and N⁺ region 20. Gate region22 covers P-region 24 of N-channel transistor 16. Also within P-well 14is N⁺ control gate 26 which includes N⁺ region 28 and N⁺ region 30. Gateregion 32 covers punch-through implant region 34. Punch-through implantregion 34 may include a phosphorous or arsenic punch through implant.Poly connection 36 connects in common gate region 22 and gate region 32.The V_(DD) pin connects to N⁺ region 18. V_(SS) connects to N⁺ region20. At N⁺ control gate 26, V_(PP) electrically connects to N⁺ region 28and N⁺ region 30. P-well 12 also includes P⁺ region 38 which connects toV_(BB). As FIG. 2 shows, during F-N erase for example, V_(DD) and V_(SS)both equal 9V, while V_(PP) and V_(BB) equal zero volts.

The formation and operation of the EEPROM 10 of the present invention issubstantially similar to that of the Ohsaki cell, however with thesignificant operational advantages of the present invention, as well asthe novel structure that includes the punch-through implant region 34.One aspect of the present invention, therefore, is the operationaladvantage that punch-through implant region 34 provides, which with theassociated elements of EEPROM 10 make possible the elimination of theN-well region of the Ohsaki Cell and similar structures to yield asmaller layout requirement for EEPROM 10.

Because of punch-through implant region 34, transistor 26 becomes an N⁺control gate for erasing. Thus, not only does the present inventionprovide the reduced layout area, but also it does so with a device thatuses a lower program voltage and a lower erase voltage than do knownsingle polysilicon flash EEPROMS.

Operationally, the present invention makes possible such results as amaximum channel hot electron (CHE) program voltage of 5V and a thresholdvoltage shift of only 2.5V after CHE program for 100 μsec. During anerase operation, the present embodiment can effectively use a maximumFowler-Nordheim (F-N) erase voltage of 9V on V_(DD) and V_(SS), with0.0V on V_(PP) and V_(BB), while achieving a threshold voltage recoverafter FN erase of approximately 1 msec. The following graphs illustratethese points.

FIG. 3 illustrates a drain current versus gate voltage times zero curvefor the structure of FIG. 1. In particular, until voltage reachesapproximately 1V, drain current remains at an approximately zero level.Thereafter, drain current increases approximately linearly at a rate ofapproximately 1.4×10⁻⁵ A/μm per volt.

FIG. 4 illustrates a drain current versus floating gate voltage timezero curve for the structure of FIG. 1. As FIG. 4 shows, until gatevoltage reaches approximately 0.5V, drain current remains at anapproximately zero level. Thereafter, drain current increases atapproximately a linear rate of 1.8×10⁻⁵ A/μm per volt.

FIG. 5 shows a curve of the drain current versus gate voltage after CHEprogramming for the structure of FIG. 1. As FIG. 5 shows, untilapproximately 3.5V, drain current remains at approximately zero amps.After approximately 3.6V, drain current increases approximately linearlyat a rate of 1.2 A/μm per volt.

FIG. 6 illustrates a plot of the floating gate voltage during CHEprogramming. As FIG. 6 shows, at 10⁻⁹ seconds, gate voltage isapproximately 4V, and decreases at an approximately constantdeceleration rate until at 10⁻⁵ seconds to a voltage of approximately2.7V. Then, the voltage decreases at a slower deceleration rate until at10⁻⁴ seconds and a voltage of 2.2V. Then, with a constant negative rate,the voltage levels to approximately 2.2V.

FIG. 7 illustrates the drain current versus gate voltage after an F-Nerase step for the structure of FIG. 1. Referring to FIG. 7, untilapproximately 0.5V, drain current maintains at a zero level. Thereafter,drain current increases at a rate of approximately 1.7×10⁻⁵ A/μm pervolt.

FIG. 8 illustrates a curve of drain voltage versus floating gate voltageafter an F-N erase step. In FIG. 8, until gate voltage reachesapproximately 0.4V, drain current remains approximately zero.Thereafter, drain current increases at a rate of approximately 2.5×10⁻⁵A/μm per volt.

Although the invention has been described in detail herein withreference to the illustrative embodiments, it is to be understood thatthis description is by way of example only and is not to be construed ina limiting sense. It is to be further understood, therefore, thatnumerous changes in the details of the embodiments of the invention andadditional embodiments of the invention, will be apparent to, and may bemade by, persons of ordinary skill in the art having reference to thisdescription. It is contemplated that all such changes and additionalembodiments are within the spirit and true scope of the invention asclaimed below.

What is claimed is:
 1. A method of operating single polysilicon memory,comprising the steps of: electrically isolating a polysilicon controlgate formed in association with an NMOS transistor and a N⁺ controlgate, said NMOS transistor and said N⁺ control gate formed in a P-welldisposed within a P-substrate, said polysilicon control gate operatingas a floating gate and in common with said NMOS transistor and said N⁺control gate; and providing a low programming and erase voltage for saidsingle polysilicon memory by operating said N⁺ control gate comprising apunch-through implant region.
 2. The method of claim 1, wherein said N⁺control gate operates with a phosphorous implant region as a controlgate.
 3. The method of claim 1, wherein said N⁺ control gate operationswith an arsenic implant region as a control gate.
 4. The method of claim1, providing a programming voltage of not greater than approximately 5volts.
 5. The method of claim 1, providing an erasing voltage of notgreater than approximately 9 volts on V_(DD) and V_(SS).
 6. The methodof claim 1, further comprising the step of programming a voltage shiftof more than approximately 2.5 volts in a period of not more thanapproximately 100 microseconds.
 7. A method of forming singlepolysilicon memory array for use in CMOS processing, comprising thesteps of: forming a P-well within a P-substrate; forming an NMOStransistor in said P-well; forming a N⁺ control gate in said P-well;forming an electrically isolated polysilicon control gate formed inassociation with said NMOS transistor and said N⁺ control gate, saidpolysilicon control gate operating as a floating gate and in common withsaid NMOS transistor and said N⁺ control gate; and further forming saidN⁺ control gate using a punch-through implant for providing a lowprogramming and erase voltage for said single polysilicon memory array.8. The method of claim 7, further comprising the step of forming said N⁺control gate comprising a phosphorous implant region.
 9. The method ofclaim 7, further comprising the step of forming said N⁺ control gatecomprising an arsenic implant region.